On Wed, 2013-04-03 at 16:40 +0800, Thierry Reding wrote: > On Wed, Apr 03, 2013 at 04:14:17PM +0800, Joseph Lo wrote: > > On Wed, 2013-04-03 at 15:54 +0800, Thierry Reding wrote: > > BTW, you can also check the minimal interval to keep the connection > > alive. For Tegra20, it need at lease 10 mS for CPU cluster power down. > > It means when CPU go into LP2, even there is an interrupt wake up him > > immediately. The CPU need to wait for power ready. It's 10mS. Only > > Tegra20 had this limitation. > > Okay, theoretically we could have something like the following sequence: > > 1) user runs "ifconfig eth0 up" > 2) driver programs network interface to bring up link > 3) driver waits for IRQ > 4) CPU goes to idle > 5) MSI is received 5.5) interrupt delivered to interrupt controller > 6) CPU is woken up by interrupt controller > 7) CPU needs 10 ms before power is ready (The 10mS is the interval for PMIC to make the power of vdd_cpu rail ready.) 8) CPU handle the ISR of MSI or R8169. I am not sure the time interval cause some functions can't work anymore on MSI or R8169. If this is the case, you may need a work around to trigger interrupt more frequently to make CPU not go into LP2 when PCIe ethernet working. BTW, the interrupt shouldn't lost, I didn't see this case before. The device interrupt was always routed to CPU0. You may check the interrupt interval in the case. And the interrupt number is still counted or not when CPU idle LP2 enabled. > No matter how long the CPU needs to wake up. Or maybe I didn't > understand what you were saying. > > Thierry > > [0]: https://gitorious.org/thierryreding/linux/blobs/tegra/next/drivers/pci/host/pci-tegra.c > > * Unknown Key > * 0x7F3EB3A1 -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
