On 03/11/2013 11:59 AM, Laxman Dewangan wrote: > On Monday 11 March 2013 11:13 PM, Stephen Warren wrote: >> On 03/09/2013 11:11 AM, Laxman Dewangan wrote: >>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which >>> supports 11x8 type of matrix. The number of rows and columns >>> are configurable. >>> >>> Add DT entry for KBC controller with compatibility as >>> "nvidia,tegra114-kbc", >>> "nvidia,tegra20-kbc". >> I thought the HW really wasn't compatible with Tegra20 due to the >> reduced number of rows/columns/pins supported? > > Hw controller is really compatible. Only thing is that there is no > physical pins on SoC for KBC-ROW11 to KBC-ROW15. > Because, there is no physical pins for ROW11 to ROW15, we asked to > remove programming/reference this rows from TRM of T114 to consistent > with SoCs. I think that makes the HW incompatible. If you only have knowledge of Tegra20/30, you can assume that there are more rows/pins/columns than there actually are. Applying those same validation restrictions on Tegra114 will yield validation that isn't strict enough; invalid values could be accepted. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html