On 01/11/2013 12:46 AM, Prashant Gaikwad wrote: > Add tegra20 clock support based on common clock framework. > diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile > +static void tegra20_pll_init(void) > + /* PLLE */ > + clk = tegra_clk_plle("pll_e", "pll_ref", clk_base, NULL, > + 0, 1000000000, &pll_e_params, > + 0, pll_e_freq_table, NULL); That 1000000000 (1GHz) needs to be 100000000 (100MHz). I can fix that up when applying this. With that change, everything I tested with this version of the series works:-) -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html