[PATCH 3/3] ARM: tegra: drm: use new EMC clock scaling API to reserve DC bandwidth

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Reserve bandwidth for the scanout to make sure EMC is not reducing DRAM
performance too far, which would cause visual corruption.

Signed-off-by: Lucas Stach <dev@xxxxxxxxxx>
---
 drivers/gpu/drm/tegra/dc.c | 11 +++++++++++
 1 Datei geändert, 11 Zeilen hinzugefügt(+)

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 0744103..8f32ebc 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <memory/tegra_emc_performance.h>
 
 #include <mach/clk.h>
 
@@ -269,6 +270,16 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc,
 	tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_NOKEY);
 	tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_1WIN);
 
+	/*
+	 * Let EMC know the bandwidth requirements of this mode.
+	 * Calculation is naive but works for now. We have to revisit this once
+	 * we support planes and dpms.
+	 */
+	value = mode->hdisplay * mode->vdisplay * bpp * drm_mode_vrefresh(mode);
+	tegra_emc_request_bandwidth(dc->pipe ?
+					TEGRA_EMC_SC_DCB : TEGRA_EMC_SC_DC,
+				    value);
+
 	return 0;
 }
 
-- 
1.7.11.7

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