On 12/02/2012 08:00 PM, Joseph Lo wrote: > The powered-down state of Tegra20 requires power gating both CPU cores. > When the secondary CPU requests to enter powered-down state, it saves > its own contexts and then enters WFI. The Tegra20 had a limition to > power down both CPU cores. The secondary CPU must waits for CPU0 in > powered-down state too. If the secondary CPU be woken up before CPU0 > entering powered-down state, then it needs to restore its CPU states > and waits for next chance. > > Be aware of that, you may see the legacy power state "LP2" in the code > which is exactly the same meaning of "CPU power down". > diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S > +/* > + * tegra_pen_lock > + * > + * spinlock implementation with no atomic test-and-set and no coherence > + * using Peterson's algorithm on strongly-ordered registers > + * used to synchronize a cpu waking up from wfi with entering lp2 on idle > + * > + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm) A link to a description of that algorithm would be useful. > + * on cpu 0: > + * SCRATCH38 = r2 = flag[0] > + * SCRATCH39 = r3 = flag[1] > + * on cpu1: > + * SCRATCH39 = r2 = flag[1] > + * SCRATCH38 = r3 = flag[0] That implies that r2/r3 are used for different purposes on the 2 CPUs, and/or shadow the values of different registers. However, I see nothing in the code which is conditional on cpu ID. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
