On Thu, Nov 15, 2012 at 08:56:17AM +0200, Terje Bergström wrote: > On 14.11.2012 22:04, Thierry Reding wrote: > > According to tegra20_clocks_data.c, the maximum clock frequency for > > host1x is 166 MHz, so 216 is probably not a good idea. 150 MHz sounds > > sensible, though. > > > > I was going to send a new version of the patch set tonight, but I'll > > wait until I can test it tomorrow and once Terje has reported back that > > things work fine. > > Hi, > > I tried with 150MHz, 133.3MHz, 100MHz and as an act of desperation > 300MHz. None of them worked. pll_p with 216MHz seems to be the only > option that works on my board. > > But, as said, this seems to affect only the case where nvhost is > integrated, too, so your patch creates a working DRM and frame buffer, > so I'm fine with leaving it as it was in the original patch set. I just tried with 150 MHz as well and it seems to work properly. So as Stephen pointed out, 144 MHz is not a supported frequency for host1x, and therefore I'll just leave the valid (and working) 150 MHz in. > Meanwhile, we need to figure out if we somehow misprogram PLLC or host1x > clock when it's attached to PLLC on Tegra20. Yes, absolutely. Among other things there's still the upcoming and much needed rework of the PLL frequency table code, so while at that we could look at the issue you're seeing as well. Thierry
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