On 14.11.2012 18:19, Stephen Warren wrote:
> I'd rather initialize it explicitly. If setting it to 216MHz works
> fine as Terje indicated, we may as well just do that.
I'd prefer explicit setting, too.
> I suspect the issue with the original code:
>
>> { "host1x", "pll_c", 144000000, false },
>
> ... is that perhaps the requested 144MHz can't be generated from
> pll_c's 600MHz rate, since there's a simple U7.1 divider there (you
> could get 120, 133.333, 150), so the clock ends up being programmed to
> some incorrect value. In the pll_p/216MHz case, pll_p is programmed to
> generate 216MHz anyway, so requesting the same rate for host1x yields
> a divider of 1 exactly which works fine.
I could try the values you proposed tomorrow when I get back to office.
I believe we've always kept host1x under non-fractional dividers, so I'd
like to try 150MHz on Ventana and 150MHz and 300MHz on Cardhu.
600MHz sounds pretty high for PLLC on Tegra20. For Tegra30 it would be
understandable. In internal kernel I believe we have lower rate for
Tegra20 PLLC. Do we have anything running from PLLC in Tegra20 upstream
kernel?
Terje
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