On Wed, Oct 31, 2012 at 2:41 AM, Joseph Lo <josephl@xxxxxxxxxx> wrote: > This supports power-gated idle on secondary CPUs for Tegra30. The > secondary CPUs can go into powered-down state independently. When > CPU goes into this state, it saves it's contexts and puts itself > to flow controlled WFI state. After that, it will been power gated. > > Be aware of that, you may see the legacy power state "LP2" in the > code which is exactly the same meaning of "CPU power down". On Tegra20, LP2 included powering off the GIC. Is that still the case for Tegra30 individual secondary cpu power gating? If so, how do IPIs to an idle cpu wake it up? -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
