Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
writes:
>> For CPU0:
>> * outer_disable (flush and disable L2)
>
> I guess L2 cannot be retained on Tegra ?
The L2 RAM is in different power domain and we do want to retain it. The
code Joseph is currently working on uses the generic outer_disable()
which will flush the L2 but eventually we want to avoid that. To
maintain coherence (and developer sanity :-) this really requires moving
the L2 disable after MMU disable and similarly moving the L2 enable
before MMU enable (keeps L2 available for TLB fetches).
--Antti
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