On 03/14/2012 09:56 AM, Thierry Reding wrote: > From: Simon Que <sque@xxxxxxxxxxxx> > > PWM clock source registers in Tegra 2 have different clock source selection bit > fields than other registers. PWM clock source bits in CLK_SOURCE_PWM_0 register > are located at bit field bit[30:28] while others are at bit field bit[31:30] in > their respective clock source register. > > This patch updates the clock programming to correctly reflect that, by adding a > flag to indicate the alternate bit field format and checking for it when > selecting a clock source (parent clock). > > Signed-off-by: Thierry Reding <thierry.reding@xxxxxxxxxxxxxxxxx> > Signed-off-by: Bill Huang <bilhuang@xxxxxxxxxx> > Signed-off-by: Simon Que <sque@xxxxxxxxxxxx> Acked-by: Stephen Warren <swarren@xxxxxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
