Thierry Reding wrote at Tuesday, December 20, 2011 3:32 AM: > From: Simon Que <sque@xxxxxxxxxxxx> > > PWM clock source registers in Tegra 2 have different clock source selection bit > fields than other registers. PWM clock source bits in CLK_SOURCE_PWM_0 register > are located at bit field bit[30:28] while others are at bit field bit[31:30] in > their respective clock source register. > > This patch updates the clock programming to correctly reflect that, by adding a > flag to indicate the alternate bit field format and checking for it when > selecting a clock source (parent clock). > > Also, adjusts for the frequency divider being offset by 1. That last line applies to the original patch in the ChromeOS tree, but not to the patch you posted (the edit to arch/arm/mach-tegra/pwm.c that was in the original patch isn't part of this patch). -- nvpublic -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
