This rate is required for correct generation of 640x480 HDMI video;
see subsequent patches.
Note: I tested the entry with 12MHz input. The other entries are untested,
but appear logically correct. However, I'm not familiar enough with PLLs
to know if they perhaps exceed the PLL VCO frequency, nor whether the
cpcon values are strictly correct.
Signed-off-by: Stephen Warren <swarren@xxxxxxxxxx>
---
arch/arm/mach-tegra/tegra2_clocks.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 41f5953..f3ead19 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1531,6 +1531,11 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
{ 19200000, 216000000, 135, 12, 1, 3},
{ 26000000, 216000000, 216, 26, 1, 4},
+ { 12000000, 252000000, 252, 12, 1, 4},
+ { 13000000, 252000000, 252, 13, 1, 4},
+ { 19200000, 252000000, 210, 16, 1, 3},
+ { 26000000, 252000000, 252, 26, 1, 4},
+
{ 12000000, 594000000, 594, 12, 1, 8},
{ 13000000, 594000000, 594, 13, 1, 8},
{ 19200000, 594000000, 495, 16, 1, 8},
--
1.7.1
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