> -----Original Message----- > From: Catalin Marinas [mailto:catalin.marinas@xxxxxxx] > Sent: Tuesday, January 25, 2011 11:44 PM > To: Russell King - ARM Linux > Cc: Colin Cross; linux-tegra@xxxxxxxxxxxxxxx; linux-arm- > kernel@xxxxxxxxxxxxxxxxxxx; olof@xxxxxxxxx; konkers@xxxxxxxxxxx; > Santosh Shilimkar; Linus Walleij; Tony Lindgren; linux- > kernel@xxxxxxxxxxxxxxx > Subject: Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support for > re-enabling l2x0 > > On Tue, 2011-01-25 at 15:41 +0000, Russell King - ARM Linux wrote: > > I think we need to come up with some proper way to deal with > cpuidle > > which doesn't involve adding lots of globally visible functions to > all > > sorts of bits of code and having platforms call them individually, > > otherwise this is going to get _really_ messy in the future. > > > > Maybe we need a notifier list which can be told when cpuidle > events > > happen, so that parts of the system such as VFP and L2 cache > support > > can do the right thing without having platforms add lots of stuff > like > > > > gic_secondary_init(); > > gic_restore_interrupt_types(); > > vfp_enable(); > > l2x0_enable(); > > twd_enable(); > > ... etc ... > > > > in their SoC specific code. > > But do we need a strict order between such operations? The notifier > call > chain isn't too flexible. > I guess it does depends on how the archs have integrated a9. Example on OMAP there are different power modes possible. 1. CPU context ,TWD lost 2. CPU context ,TWD + L1 is lost 3. CPU context + L1 is lost + GIC lost 4. CPU context + L1 is lost + GIC lost + L2 lost So there is need to have flexibility of calling these function based on power modes. I don't know how notifiers can give this flexibility Regards, Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html