Mark,
wm8903_set_bias_level() sets register bit WM8903_CLK_SYS_ENA
when entering SND_SOC_BIAS_STANDBY from _OFF. This requires
that MCLK is running to the codec for register access to
work per the datasheet (and in practice, I hear no sound if
MCLK was not running then. Since this _BIAS_ transition
happens during wm8903_probe, it happens before any code in
the Harmony ASoC machine driver has had a chance to enable
the Tegra cdev1 clock output, fed to the WM8903 MCLK.
In practice, this means:
* arch/arm/mach-tegra/board-harmony.c must contain the
following to enable cdev1/MCLK early enough:
static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
...
{ "pll_a", "pll_p_out1", 56448000, true},
{ "pll_a_out0", "pll_a", 11289600, true},
{ "cdev1", "pll_a_out0", 11289600, true},
* The Harmony driver probably shouldn't ever disable the cdev1
clock output, except for short durations within a single
function, since the WM8903 may need this clock for register
access at arbitrary times.
This means the Harmony machine driver can't really disable/
enable cdev1/MCLK solely when an audio stream is open or
actively streaming, as I was intending.
Is this intended; should the WM8903 driver not be enabling
SYS_ENA so broadly. Perhaps e.g. it should only be enabled
during SND_SOC_BIAS_ON/_PREPARE, and not during _STANDBY?
Alternatively, would having the Harmony machine driver
implement a set_bias function help working around this?
Thanks.
--
nvpublic
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