On Thu, Sep 16, 2010 at 11:27 PM, Colin Cross <ccross@xxxxxxxxxx> wrote:
> On Thu, Sep 16, 2010 at 9:53 AM, Mike Rapoport <mike@xxxxxxxxxxxxxx> wrote:
>> Signed-off-by: Mike Rapoport <mike@xxxxxxxxxxxxxx>
>> ---
>> arch/arm/mach-tegra/tegra2_clocks.c | 76 +++++++++++++++++++++++++++++++++-
>> 1 files changed, 73 insertions(+), 3 deletions(-)
>
> <snip>
>
>> -static int tegra2_pll_clk_wait_for_lock(struct clk *c)
>> +static int tegra2_pll_clk_wait_for_bit_set(struct clk *c, int bit)
>> {
>> ktime_t before;
>>
>> before = ktime_get();
>> - while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
>> + while (!(clk_readl(c->reg + PLL_BASE) & bit)) {
>> if (ktime_us_delta(ktime_get(), before) > 5000) {
>> pr_err("Timed out waiting for lock bit on pll %s",
>> c->name);
>> @@ -414,7 +416,7 @@ static int tegra2_pll_clk_enable(struct clk *c)
>> val |= PLL_MISC_LOCK_ENABLE;
>> clk_writel(val, c->reg + PLL_MISC(c));
>>
>> - tegra2_pll_clk_wait_for_lock(c);
>> + tegra2_pll_clk_wait_for_bit_set(c, PLL_BASE_LOCK);
>>
>> return 0;
>> }
>
> I've been told by Nvidia that the pll lock bits are not reliable, and
> will be removing uses of tegra2_pll_clk_wait_for_lock and replacing
> them with delays selected by each pll. Can you confirm with Nvidia
> that PLLE_MISC_READY works?
I'll try to get a confirmation from NVidia....
>From what I've seen during testing the PLLE_MISC_READY works. When I
used loops that counted udelay(1) I've noticed that the
PLLE_MISC_READY is set after up to 3usecs.
> <snip>
>
>> +static struct clk_ops tegra_pcie_clk_ops = {
>> + .enable = tegra2_periph_clk_enable,
>> + .disable = tegra2_periph_clk_disable,
>> +};
> Why is this needed? Won't the regular periph ops work?
They didn't. I haven't found anything about what feeds these clocks,
can they change rate, what clock can be their parent and if there is
any muxing options for these clocks.
> <snip>
>
>> +static struct clk tegra_clk_pex = {
>> + .name = "pex",
>> + .flags = PERIPH_MANUAL_RESET,
>> + .ops = &tegra_pcie_clk_ops,
>> + .clk_num = 70,
>> +};
>> +
>> +static struct clk tegra_clk_afi = {
>> + .name = "afi",
>> + .flags = PERIPH_MANUAL_RESET,
>> + .ops = &tegra_pcie_clk_ops,
>> + .clk_num = 72,
>> +};
>> +
>> +/* the pcie_xclk is required for reset of PCIE subsystem */
>> +static struct clk tegra_clk_pcie_xclk = {
>> + .name = "pcie_xclk",
>> + .clk_num = 74,
>> +};
> These should probably all be defined in the CLK_PERIPH table.
See the comment above :)
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>
--
Sincerely Yours,
Mike.
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