The cache-line-size is cached in struct vchiq_platform_info.
There is no need to cache this again via g_cache_line_size
and use it. Instead use the value from vchiq_platform_info directly.
While at it, move the comment about L2 cache line size in the kerneldoc
block of struct vchiq_platform_info.
Signed-off-by: Umang Jain <umang.jain@xxxxxxxxxxxxxxxx>
Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
---
.../interface/vchiq_arm/vchiq_arm.c | 34 ++++++++-----------
.../interface/vchiq_arm/vchiq_arm.h | 15 ++++++++
2 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
index 9273767f25df..0dffc36dccd7 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
@@ -131,17 +131,6 @@ struct vchiq_pagelist_info {
};
static void __iomem *g_regs;
-/* This value is the size of the L2 cache lines as understood by the
- * VPU firmware, which determines the required alignment of the
- * offsets/sizes in pagelists.
- *
- * Modern VPU firmware looks for a DT "cache-line-size" property in
- * the VCHIQ node and will overwrite it with the actual L2 cache size,
- * which the kernel must then respect. That property was rejected
- * upstream, so we have to use the VPU firmware's compatibility value
- * of 32.
- */
-static unsigned int g_cache_line_size = 32;
static unsigned int g_fragments_size;
static char *g_fragments_base;
static char *g_free_fragments;
@@ -212,6 +201,7 @@ static struct vchiq_pagelist_info *
create_pagelist(struct vchiq_instance *instance, char *buf, char __user *ubuf,
size_t count, unsigned short type)
{
+ struct vchiq_drv_mgmt *drv_mgmt;
struct pagelist *pagelist;
struct vchiq_pagelist_info *pagelistinfo;
struct page **pages;
@@ -226,6 +216,8 @@ create_pagelist(struct vchiq_instance *instance, char *buf, char __user *ubuf,
if (count >= INT_MAX - PAGE_SIZE)
return NULL;
+ drv_mgmt = dev_get_drvdata(instance->state->dev->parent);
+
if (buf)
offset = (uintptr_t)buf & (PAGE_SIZE - 1);
else
@@ -368,9 +360,9 @@ create_pagelist(struct vchiq_instance *instance, char *buf, char __user *ubuf,
/* Partial cache lines (fragments) require special measures */
if ((type == PAGELIST_READ) &&
- ((pagelist->offset & (g_cache_line_size - 1)) ||
+ ((pagelist->offset & (drv_mgmt->info->cache_line_size - 1)) ||
((pagelist->offset + pagelist->length) &
- (g_cache_line_size - 1)))) {
+ (drv_mgmt->info->cache_line_size - 1)))) {
char *fragments;
if (down_interruptible(&g_free_fragments_sema)) {
@@ -396,12 +388,15 @@ static void
free_pagelist(struct vchiq_instance *instance, struct vchiq_pagelist_info *pagelistinfo,
int actual)
{
+ struct vchiq_drv_mgmt *drv_mgmt;
struct pagelist *pagelist = pagelistinfo->pagelist;
struct page **pages = pagelistinfo->pages;
unsigned int num_pages = pagelistinfo->num_pages;
dev_dbg(instance->state->dev, "arm: %pK, %d\n", pagelistinfo->pagelist, actual);
+ drv_mgmt = dev_get_drvdata(instance->state->dev->parent);
+
/*
* NOTE: dma_unmap_sg must be called before the
* cpu can touch any of the data/pages.
@@ -417,10 +412,10 @@ free_pagelist(struct vchiq_instance *instance, struct vchiq_pagelist_info *pagel
g_fragments_size;
int head_bytes, tail_bytes;
- head_bytes = (g_cache_line_size - pagelist->offset) &
- (g_cache_line_size - 1);
+ head_bytes = (drv_mgmt->info->cache_line_size - pagelist->offset) &
+ (drv_mgmt->info->cache_line_size - 1);
tail_bytes = (pagelist->offset + actual) &
- (g_cache_line_size - 1);
+ (drv_mgmt->info->cache_line_size - 1);
if ((actual >= 0) && (head_bytes != 0)) {
if (head_bytes > actual)
@@ -435,8 +430,8 @@ free_pagelist(struct vchiq_instance *instance, struct vchiq_pagelist_info *pagel
(tail_bytes != 0))
memcpy_to_page(pages[num_pages - 1],
(pagelist->offset + actual) &
- (PAGE_SIZE - 1) & ~(g_cache_line_size - 1),
- fragments + g_cache_line_size,
+ (PAGE_SIZE - 1) & ~(drv_mgmt->info->cache_line_size - 1),
+ fragments + drv_mgmt->info->cache_line_size,
tail_bytes);
down(&g_free_fragments_mutex);
@@ -479,8 +474,7 @@ static int vchiq_platform_init(struct platform_device *pdev, struct vchiq_state
if (err < 0)
return err;
- g_cache_line_size = drv_mgmt->info->cache_line_size;
- g_fragments_size = 2 * g_cache_line_size;
+ g_fragments_size = 2 * drv_mgmt->info->cache_line_size;
/* Allocate space for the channels in coherent memory */
slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE);
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h
index 04683d98cd00..378415b205ef 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h
@@ -27,6 +27,21 @@ enum USE_TYPE_E {
USE_TYPE_VCHIQ
};
+/**
+ * struct vchiq_platform_info - Platform information related to
+ * underlying hardware.
+ *
+ * @cache_line_size: value of L2 cache line
+ *
+ * cache_line_size is the size of the L2 cache lines as understood by the
+ * VPU firmware, which determines the required alignment of the offsets/sizes
+ * in pagelists.
+ *
+ * Modern VPU firmware looks for a DT "cache-line-size" property in the
+ * VCHIQ node and will overwrite it with the actual L2 cache size, which
+ * the kernel must then respect. That property was rejected upstream, so
+ * we use a value derived from the compatible string.
+ */
struct vchiq_platform_info {
unsigned int cache_line_size;
};
--
2.43.0
