On Sun, Nov 20, 2022 at 01:24:21AM +0530, Deepak R Varma wrote: > The DCCFreq value is used to obtain the DC offset canceller cut-off > frequency. Upon device power reset, the bits 7-5 of the RegRxBw register > that represent the DCCFreq setting are set to 0x4, which evaluates the > cut-off frequency to be 1% of RxBw. > > In the current implementation, first, there is no configuration variable > defined in the struct pi433_rx_cfg for the user to set this value as > part of the UAPI. Second, the code simply ignores the value of DCC > setting and allows it to never change. > > As per the RFM69HCW tech specs, the default value for DCC frequency is > recommended to be 4% of the RxBw; which requires the DCC setting bits > to be set to 010. So allow the DCC setting to change to recommended / > default value for improved rx sensitivity. > > Signed-off-by: Deepak R Varma <drv@xxxxxxxxx> > --- > > Please Note: The proposed change is compile tested only. I am unable to perform > device based testing in the absence of the hardware, both the RasPi board and the > Pi433 device. Please let me know if it is necessary for me to test such patches > on the real device myself. I will stop sending the patches till I have the hardware > to test them. Thanks. For changes like this, you need to test it on the device itself. thanks, greg k-h
