Hi Paul, On Tue, Jul 19, 2022 at 12:04:31PM +0200, Paul Kocialkowski wrote: > Hi Sakari, > > On Sun 17 Jul 22, 11:37, Sakari Ailus wrote: > > Hi Paul, > > > > On Mon, Jul 04, 2022 at 07:35:18PM +0200, Paul Kocialkowski wrote: > > > This introduces YAML bindings documentation for the Allwinner A31 Image > > > Signal Processor (ISP). > > > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx> > > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > > --- > > > .../media/allwinner,sun6i-a31-isp.yaml | 97 +++++++++++++++++++ > > > 1 file changed, 97 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml > > > new file mode 100644 > > > index 000000000000..2fda6e05e16c > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml > > > @@ -0,0 +1,97 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-isp.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Allwinner A31 Image Signal Processor Driver (ISP) Device Tree Bindings > > > + > > > +maintainers: > > > + - Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx> > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - allwinner,sun6i-a31-isp > > > + - allwinner,sun8i-v3s-isp > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + clocks: > > > + items: > > > + - description: Bus Clock > > > + - description: Module Clock > > > + - description: DRAM Clock > > > + > > > + clock-names: > > > + items: > > > + - const: bus > > > + - const: mod > > > + - const: ram > > > + > > > + resets: > > > + maxItems: 1 > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: CSI0 input port > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: CSI1 input port > > > > Do both support a single PHY with a single data only? If multiple data lanes > > are supported, please require data-lanes property (on endpoint). > > There's actually no PHY involved here: the ISP drivers gets its video stream > from these CSI controllers which are the ones interfacing with a MIPI CSI-2 > receiver (on A31/V3 it uses an external D-PHY, on A83T the D-PHY is collocated > with the controller). > > So I think the data-lanes property is not relevant here. > > What do you think? Ah, indeed, if it's an internal bus, then data-lanes isn't relevant. -- Sakari Ailus
