Hi Moses,
Thank you for the patch.
On Fri, Jan 21, 2022 at 11:51:11AM +0100, Moses Christopher Bollavarapu wrote:
> There is a BIT(nr) macro available in Linux Kernel,
> which does the same thing.
>
> Example: 1 << 7 is same as BIT(7)
>
> Signed-off-by: Moses Christopher Bollavarapu <mosescb.dev@xxxxxxxxx>
> Reviewed-by: Dan Carpenter <dan.carpenter@xxxxxxxxxx>
Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> ---
> V2 -> V3: Add Dan's Reviewed-by tag to commit message
> V1 -> V2: Use BIT(0) instead of 1
>
> drivers/staging/media/omap4iss/iss_video.h | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/staging/media/omap4iss/iss_video.h b/drivers/staging/media/omap4iss/iss_video.h
> index 526281bf0051..1724ed03ce9d 100644
> --- a/drivers/staging/media/omap4iss/iss_video.h
> +++ b/drivers/staging/media/omap4iss/iss_video.h
> @@ -53,19 +53,19 @@ enum iss_pipeline_stream_state {
>
> enum iss_pipeline_state {
> /* The stream has been started on the input video node. */
> - ISS_PIPELINE_STREAM_INPUT = 1,
> + ISS_PIPELINE_STREAM_INPUT = BIT(0),
> /* The stream has been started on the output video node. */
> - ISS_PIPELINE_STREAM_OUTPUT = (1 << 1),
> + ISS_PIPELINE_STREAM_OUTPUT = BIT(1),
> /* At least one buffer is queued on the input video node. */
> - ISS_PIPELINE_QUEUE_INPUT = (1 << 2),
> + ISS_PIPELINE_QUEUE_INPUT = BIT(2),
> /* At least one buffer is queued on the output video node. */
> - ISS_PIPELINE_QUEUE_OUTPUT = (1 << 3),
> + ISS_PIPELINE_QUEUE_OUTPUT = BIT(3),
> /* The input entity is idle, ready to be started. */
> - ISS_PIPELINE_IDLE_INPUT = (1 << 4),
> + ISS_PIPELINE_IDLE_INPUT = BIT(4),
> /* The output entity is idle, ready to be started. */
> - ISS_PIPELINE_IDLE_OUTPUT = (1 << 5),
> + ISS_PIPELINE_IDLE_OUTPUT = BIT(5),
> /* The pipeline is currently streaming. */
> - ISS_PIPELINE_STREAM = (1 << 6),
> + ISS_PIPELINE_STREAM = BIT(6),
> };
>
> /*
> @@ -119,9 +119,9 @@ struct iss_buffer {
>
> enum iss_video_dmaqueue_flags {
> /* Set if DMA queue becomes empty when ISS_PIPELINE_STREAM_CONTINUOUS */
> - ISS_VIDEO_DMAQUEUE_UNDERRUN = (1 << 0),
> + ISS_VIDEO_DMAQUEUE_UNDERRUN = BIT(0),
> /* Set when queuing buffer to an empty DMA queue */
> - ISS_VIDEO_DMAQUEUE_QUEUED = (1 << 1),
> + ISS_VIDEO_DMAQUEUE_QUEUED = BIT(1),
> };
>
> #define iss_video_dmaqueue_flags_clr(video) \
--
Regards,
Laurent Pinchart
