在 2021/12/16 14:18, Arnd Bergmann 写道:
On Thu, Dec 16, 2021 at 3:14 PM Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote:
在 2021/12/16 13:50, Arnd Bergmann 写道:
On Thu, Dec 16, 2021 at 2:07 PM Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote:
在2021年12月16日十二月 上午11:44，Xi Ruoyao写道：
Another way could be keeping a linked list about PIO->PHYS mapping instead of using the single io_port_base variable.
I think that would add a lot of complexity that isn't needed here. Not
sure if all MIPS CPUs
can do it, but the approach used on Arm is what fits in best with the
PCI drivers, these
reserve a virtual address range for the ports, and ioremap the
physical addresses into
the PIO range according to the mapping.
Yes, the Arm way was my previous approach when introducing PCI IO map
for Loongson.
It got refactored by this patch as TLB entries are expensive on MIPS,
also the size of IO range doesn't always fits a page.
Are PIO accesses common enough that the TLB entry makes a difference?
I would imagine that on most systems with a PCI bus, there is not even
a single device that exposes an I/O resource, and even on those devices that
do, the kernel drivers tend to pick MMIO whenever both are available.
Actually that was claimed by the author of this patch :-)
I can understand the point. As he is working on a ramips system utlizes
1004Kec,
which has only 32 TLB entries, saving a entry can give considerable
improvement.
For Loongson as we have legacy i8042/i8259 which can only be accessed via
PIO, the access is very common.
For other systems I guess it's not that common.
Thanks.
Arnd
- Jiaxun
