Hi Dafna,
On Tue, 14 Dec 2021 at 16:48, Dafna Hirschfeld
<dafna.hirschfeld@xxxxxxxxxxxxx> wrote:
> >>> +static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, int timeout, unsigned int addr)
> >>> +{
> >>> + u32 gdi_status_check_value = 0x3f;
> >>> + u32 data;
> >>> +
> >>> + if (vpu_dev->product_code == WAVE521C_CODE ||
> >>> + vpu_dev->product_code == WAVE521_CODE ||
> >>> + vpu_dev->product_code == WAVE521E1_CODE)
> >>> + gdi_status_check_value = 0x00ff1f3f;
> >>> +
> >>> + return read_poll_timeout(wave5_vdi_read_register, data, data == gdi_status_check_value,
> >>> + 0, timeout * 1000, false, vpu_dev, addr);
> >>> +}
> >>> +
> >>
> >> This looks like it should be s/wave5_vdi_read_register/wave5_read_register/.
> >> For wave511 addr passed in here is 0x8e14 so well outside of what is
> >> directly accessible.
> >
> > Hi, I didn't understand this explanation. I see that
> > wave5_read_register eventually calls 'wave5_vdi_read_register'.
> > Could you please explain in more detail why you think
> > calling wave5_vdi_read_register is wrong?
Mainly because the address accessed 0x8e14 but on my machine the
directly accessible registers end at 0x800.
> hi, I see know that those backbone address are indeed not read and written directly but
> the address should be first written to a regsiter W5_VPU_FIO_CTRL_ADDR,
> and then the content is returned from W5_VPU_FIO_DATA.
I think so. But as I can't get this driver to fully work yet I can
only say I think so.
Cheers,
Daniel
