Quoting Andrew Lunn <andrew@xxxxxxx>:
On Thu, Apr 08, 2021 at 11:00:08PM +0800, DENG Qingfang wrote:
Hi René,
On Thu, Apr 8, 2021 at 10:02 PM René van Dorst
<opensource@xxxxxxxxxx> wrote:
>
> Tested on Ubiquiti ER-X-SFP (MT7621) with 1 external phy which
uses irq=POLL.
>
I wonder if the external PHY's IRQ can be registered in the devicetree.
Change MT7530_NUM_PHYS to 6, and add the following to ER-X-SFP dts PHY node:
I don't know this platform. What is the PHYs interrupt pin connected
to? A SoC GPIO? There is a generic mechanism to describe PHY
interrupts in DT. That should be used, if it is a GPIO.
Andrew
Quoting Andrew Lunn <andrew@xxxxxxx>:
On Thu, Apr 08, 2021 at 11:00:08PM +0800, DENG Qingfang wrote:
Hi René,
On Thu, Apr 8, 2021 at 10:02 PM René van Dorst
<opensource@xxxxxxxxxx> wrote:
>
> Tested on Ubiquiti ER-X-SFP (MT7621) with 1 external phy which
uses irq=POLL.
>
I wonder if the external PHY's IRQ can be registered in the devicetree.
Change MT7530_NUM_PHYS to 6, and add the following to ER-X-SFP dts PHY node:
I don't know this platform. What is the PHYs interrupt pin connected
to? A SoC GPIO? There is a generic mechanism to describe PHY
interrupts in DT. That should be used, if it is a GPIO.
Andrew
Hi Andrew,
I couldn't find if the external phy IRQ is connected to any gpio of the SOC.
So External PHY IRQ can't be sensed via a gpio.
The patch used the MT7530 link change interrupt and flags.
Maybe the patch is misusing the these flags as an interrupt?
The same MT7530 register also has the interrupt flags for the internal phys.
But in the MT7531 datasheet they don't describe them.
On the other hand I don't have any information about the internal PHY
or register settings.
So enabling the interrupt on the PHY is currently not possible.
I also forced enabled all the MT7530 PHY interrupts and PHY link
change interrupts.
I print the interrupt status mt7530.
I don't see any MT7530 interrupt fired when link changing the port
5/external phy.
Which was of course as expected. We only have 5 internal phy's for the
port 0 to 4.
Port 5 and 6 is only have a MAC that is connected to the SOC of an
external PHY.
Greats,
René
