On Wed, Mar 19, 2025 at 01:58:38PM +0000, Rengarajan.S@xxxxxxxxxxxxx wrote: > Hi Mark, > > Thanks for reviewing the patch and apologies for delayed response. > > On Mon, 2025-02-24 at 14:30 +0000, Mark Brown wrote: > > [Some people who received this message don't often get email from > > broonie@xxxxxxxxxx. Learn why this is important at > > https://aka.ms/LearnAboutSenderIdentification ] > > > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > know the content is safe You have not quoted any context from the message you're replying to so I don't really know what you're talking about. > I went through several patches related to similar issues, and mostsuggest handling it on a SoC basis. The reasoning is that a system > may have an affected PCIe root complex while still having other > devices in the SoC that can, or even require, 64-bit accesses. > The following are some of the patches that I had looked into: > https://lore.kernel.org/lkml/20210226140305.26356-2-nsaenzjulienne@xxxxxxx/T/#u That's a adding a generic 64bit-mmio-broken property - that's an example of something that's not quirking off the SoC compatible. Doesn't seem to have reached mainline though. > https://lore.kernel.org/linux-arm-kernel/c188698ca0de3ed6c56a0cf7880e1578aa753077.camel@xxxxxxx/T/#u > Can you please suggest any alternate methods that we could use to > handle this in a more generic manner instead of making it Soc-specific. That thread seems to be going down a similar direction - adding a generic quirk that the accesses are broken. Both these threads seem to be suggesting something like what I was thinking of, you've got a generic DT property or some other indication that the device can't use 64 bit accesses on this platform.
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