On Wed, Feb 12, 2025 at 02:46:48PM +0000, Vishwaroop A wrote:
> This patch corrects the QSPI_COMMAND_X1_X2_X4 and QSPI_ADDRESS_X1_X2_X4
> macros to properly encode the bus width for x1, x2, and x4 transfers.
> Although these macros were previously incorrect, they were not being
> used in the driver, so no functionality was affected.
>
> The patch updates tegra_qspi_cmd_config() and tegra_qspi_addr_config()
> function calls to use the actual bus width from the transfer, instead of
> hardcoding it to 0 (which implied x1 mode). This change enables proper
> support for x1, x2, and x4 data transfers by correctly configuring the
> interface width for commands and addresses.
>
> These modifications improve the QSPI driver's flexibility and prepare it
> for future use cases that may require different bus widths for commands
> and addresses.
>
> Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode")
>
> Signed-off-by: Vishwaroop A <va@xxxxxxxxxx>
With that blank line between Fixes: and S-o-b: dropped, this is:
Acked-by: Thierry Reding <treding@xxxxxxxxxx>
Attachment:
signature.asc
Description: PGP signature
