On 1/29/25 08:40, Krzysztof Kozlowski wrote: > On Tue, Jan 28, 2025 at 06:02:27PM +0000, Conor Dooley wrote: >>> + st,syscfg-dlyb: >>> + description: phandle to syscon block >>> + Use to set the OSPI delay block within syscon to >>> + tune the phase of the RX sampling clock (or DQS) in order >>> + to sample the data in their valid window and to >>> + tune the phase of the TX launch clock in order to meet setup >>> + and hold constraints of TX signals versus the memory clock. >>> + $ref: /schemas/types.yaml#/definitions/phandle-array >> >> Why do you need a phandle here? I assume looking up by compatible ain't >> possible because you have multiple controllers on the SoC? Also, I don't >> think your copy-paste "phandle to" stuff here is accurate: >> st,syscfg-dlyb = <&syscfg 0x1000>; >> There's an offset here that you don't mention in your description. > > This needs double items: and listing them with description, instead of > free form text. ok, i will remove most of ths text description and update as following : st,syscfg-dlyb: description: configure OCTOSPI delay block. $ref: /schemas/types.yaml#/definitions/phandle-array items: - description: phandle to syscfg - description: register offset within syscfg Thanks Patrice > > Best regards, > Krzysztof >