AMD SPI controller’s index mode performance is constrained by the hardware limitation of the FIFO queue length. This patch series introduces optimizations to the spi_amd driver, aiming to maximize throughput and enhance overall performance. The changes includes, - Enable SPI dual and quad I/O modes and update SPI-MEM support function to reflect AMD SPI0 hardware capabilities. - Utilize efficient kernel APIs to streamline SPI I/O operations for enhanced performance. - Refine the set tx/rx count functions to optimize SPI I/O throughput. - Minimize the number of data read calls by efficiently retrieving data from FIFO queues, improving SPI I/O efficiency. - Add changes to support AMD HID2 SPI controller and update SPI-MEM support function to reflect AMD HID2 hardware capabilities. - Add changes to set SPI controller address mode before initiating the commands - Add changes to implement HIDDMA read operation support for HID2 SPI controller V1->V2: ------- - Eliminate the separate patch that introduces SPI-MEM support function modifications, and incorporate those changes into the existing patches for enabling dual and quad I/O modes, as well as enhance support for the HID2 SPI controller. Raju Rangoju (8): spi: spi_amd: Sort headers alphabetically spi: spi_amd: Enable dual and quad I/O modes spi: spi_amd: Replace ioread/iowrite calls spi: spi_amd: Updates to set tx/rx count functions spi: spi_amd: Optimize IO operations spi: spi_amd: Add support for HID2 SPI controller spi: spi_amd: Set controller address mode spi: spi_amd: Add HIDDMA basic read support drivers/spi/spi-amd.c | 325 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 295 insertions(+), 30 deletions(-) -- 2.34.1