On Wed, Sep 18, 2024 at 10:27:43AM +0200, Alexander Dahl wrote:
> Previously the MR and SCR registers were just set with the supposedly
> required values, from cached register values (cached reg content
> initialized to zero).
>
> All parts fixed here did not consider the current register (cache)
> content, which would make future support of cs_setup, cs_hold, and
> cs_inactive impossible.
>
> Setting SCBR in atmel_qspi_setup() erases a possible DLYBS setting from
> atmel_qspi_set_cs_timing(). The DLYBS setting is applied by ORing over
> the current setting, without resetting the bits first. All writes to MR
> did not consider possible settings of DLYCS and DLYBCT.
>
> Signed-off-by: Alexander Dahl <ada@xxxxxxxxxxx>
> Fixes: f732646d0ccd ("spi: atmel-quadspi: Add support for configuring CS timing")
This isn't actually a fix AFAICT since nothing yet sets any of these
fields?
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