Check SPI access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Signed-off-by: Alexander Usyskin <alexander.usyskin@xxxxxxxxx> --- drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 ++++ drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +--- drivers/gpu/drm/xe/xe_spi.c | 33 ++++++++++++++++++++++++++- 3 files changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h index 7702364b65f1..9b66cc972a63 100644 --- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h @@ -16,6 +16,10 @@ #define MTL_GSC_HECI1_BASE 0x00116000 #define MTL_GSC_HECI2_BASE 0x00117000 +#define DG1_GSC_HECI2_BASE 0x00259000 +#define PVC_GSC_HECI2_BASE 0x00285000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define HECI_H_CSR(base) XE_REG((base) + 0x4) #define HECI_H_CSR_IE REG_BIT(0) #define HECI_H_CSR_IS REG_BIT(1) diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c index 65b2e147c4b9..27734085164e 100644 --- a/drivers/gpu/drm/xe/xe_heci_gsc.c +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c @@ -11,14 +11,11 @@ #include "xe_device_types.h" #include "xe_drv.h" #include "xe_heci_gsc.h" +#include "regs/xe_gsc_regs.h" #include "xe_platform_types.h" #define GSC_BAR_LENGTH 0x00000FFC -#define DG1_GSC_HECI2_BASE 0x259000 -#define PVC_GSC_HECI2_BASE 0x285000 -#define DG2_GSC_HECI2_BASE 0x374000 - static void heci_gsc_irq_mask(struct irq_data *d) { /* generic irq handling */ diff --git a/drivers/gpu/drm/xe/xe_spi.c b/drivers/gpu/drm/xe/xe_spi.c index 37080b82e9ae..8ac6376f663e 100644 --- a/drivers/gpu/drm/xe/xe_spi.c +++ b/drivers/gpu/drm/xe/xe_spi.c @@ -5,7 +5,10 @@ #include <linux/intel_dg_spi_aux.h> #include <linux/pci.h> +#include "xe_device.h" #include "xe_device_types.h" +#include "xe_mmio.h" +#include "regs/xe_gsc_regs.h" #include "xe_spi.h" #include "xe_sriov.h" @@ -24,6 +27,34 @@ static void xe_spi_release_dev(struct device *dev) { } +static bool xe_spi_writeable_override(struct xe_device *xe) +{ + struct xe_gt *gt = xe_root_mmio_gt(xe); + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); + resource_size_t base; + bool writeable_override; + + if (xe->info.platform == XE_BATTLEMAGE) { + base = DG2_GSC_HECI2_BASE; + } else if (xe->info.platform == XE_PVC) { + base = PVC_GSC_HECI2_BASE; + } else if (xe->info.platform == XE_DG2) { + base = DG2_GSC_HECI2_BASE; + } else if (xe->info.platform == XE_DG1) { + base = DG1_GSC_HECI2_BASE; + } else { + dev_err(&pdev->dev, "Unknown platform\n"); + return true; + } + + writeable_override = + !(xe_mmio_read32(>->mmio, HECI_H_GS1(base)) & + HECI_FW_STATUS_2_SPI_ACCESS_MODE); + if (writeable_override) + dev_info(&pdev->dev, "SPI access overridden by jumper\n"); + return writeable_override; +} + void xe_spi_init(struct xe_device *xe) { struct intel_dg_spi_dev *spi = &xe->spi; @@ -38,7 +69,7 @@ void xe_spi_init(struct xe_device *xe) if (IS_SRIOV_VF(xe)) return; - spi->writeable_override = false; + spi->writeable_override = xe_spi_writeable_override(xe); spi->bar.parent = &pdev->resource[0]; spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start; spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1; -- 2.34.1