Hi Michael,
On 7/26/24 14:55, Michael Walle wrote:
Hi,
Based on the inputs/suggestions from Tudor, i am planning to add a new
layer between the SPI-NOR and MTD layers to support stacked and parallel
configurations. This new layer will be part of the spi-nor and located in
mtd/spi-nor/
Will AMD submit to maintain this layer? What happens if the
maintainer will leave AMD? TBH, personally, I don't like to
maintain such a niche feature.
I'd really like to see some use cases and performance reports for
this, like actual boards (and no evaluation boards don't count). Why
wouldn't someone just use an octal flash?
AMD/Xilinx is not creating products that's why we don't have data on actual
boards but I don't really understand why evaluation boards don't count. A lot of
customers are taking schematics from us and removing parts which they don't need
and add their custom part.
But one product for parallel configuration which is publicly saying that it is
using it is for example this SOM.
https://shop.trenz-electronic.de/en/TE0820-05-2AI21MA-MPSoC-Module-with-AMD-Zynq-UltraScale-ZU2CG-1I-2-GByte-DDR4-SDRAM-4-x-5-cm
I am not marketing guy to tell if there is any other which publicly saying we
are using this feature but we can only develop/support/maintain support for
these configurations on our evaluation boards because that's what we have access
to and what we know how it is done.
Also performance numbers from us can be only provided against our evaluation boards.
Thanks,
Michal
