From: AlvinZhou <alvinzhou@xxxxxxxxxxx> Add method for Macronix Octal DTR Eable/Disable. Merge Tudor's patch "Allow specifying the byte order in DTR mode" v9: Change the name of the configuration register 2 for Macronix Octal flash. Fix the bit value in __pad of struct spi_mem_op. Use the local variable proto instead of nor->read_proto. v8: Supplement missing S-o-b Remove function spi_nor_is_octal_dtr_swab16 Split IDs by MX25 & MX66 Add dump of capability in debugfs Add dump of params in debugfs Add dump of reult for mtd-utils tests Add SNOR_ID(0xC2) in last of Macronix ID table v7: Add dtr_swab16 judgement to enable/disable Macronix xSPI host controller swap byte feature. v6: Add byte swap support for spi-mxic.c Remove flash name in ID table. v5: Remove manufacturer read id function. For increased readability, separate Flash IDs based on whether it supports RWW feature. v4: Add patch for adding manufacturer read id function. remove patch "hook manufacturer by checking first byte id" v3: Add patch for hook manufacturer by comparing ID 1st byte. Add patches for specifying the byte order in DTR mode by merging Tudor's patch. v2: Following exsting rules to re-create Macronix specify Octal DTR method. change signature to jaimeliao@xxxxxxxxxxx Clear sector size information in flash INFO. AlvinZhou (6): mtd: spi-nor: add Octal DTR support for Macronix flash spi: spi-mem: Allow specifying the byte order in Octal DTR mode mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT spi: mxic: Add support for swapping byte mtd: spi-nor: add support for Macronix Octal flash drivers/mtd/spi-nor/core.c | 4 ++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/macronix.c | 95 +++++++++++++++++++++++++++++++++- drivers/mtd/spi-nor/sfdp.c | 4 ++ drivers/mtd/spi-nor/sfdp.h | 1 + drivers/spi/spi-mem.c | 3 ++ drivers/spi/spi-mxic.c | 17 ++++-- include/linux/spi/spi-mem.h | 8 ++- 8 files changed, 127 insertions(+), 6 deletions(-) -- 2.25.1