On Mon, Jul 01, 2024 at 03:10:54PM -0300, Marcelo Schmitt wrote:
> On 06/30, Jonathan Cameron wrote:
> > Marcelo Schmitt <marcelo.schmitt@xxxxxxxxxx> wrote:
> > > + struct spi_transfer t = {
> > > + .tx_buf = st->tx_buf,
> > > + .rx_buf = st->rx_buf,
> > > + .len = 2,
> > > + };
> > I'd be tempted to do
> > ssize_t ret;
> >
> > ret = spi_w8r8(AD4000_READ_COMMAND);
> I tried this when working on v6. Only difference was I had declared ret as int.
> Then reg values were not read correctly with spi_w8r8().
> I'm either missing something or reg access must be 16-bit transfer.
> Datasheet sais:
> "The AD4000/AD4004/AD4008 configuration register is read from and written to
> with a 16-bit SPI instruction."
> Yet, besides possible delay between first and last 8 SCLK pulses, I don't see
> any transfer level differences between current and spi_w8r8() versions.
It is possible the chip gets upset with the state of the idle line
during the RX only or TX only portion of the transfer.
>
> >
> >
> ...
> > > + ret = ad4000_write_reg(st, reg_val);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + st->span_comp = span_comp_en;
> > > + return ret;
> >
> > If you are spinning for another reason, make it clear this is always good.
> > The spi_write() never returns positive so current code is correct but I had
> > to go check which this would have avoided.
> >
> > return 0;
>
> Ack
> >
> > If nothing else comes up, I'll probably tweak whilst applying.
> >
> > J
> >
> > > + }
> > > + unreachable();
> > > + default:
> > > + return -EINVAL;
> > > + }
> > > +}
> >
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