The PolarFire SoC SPI controller supports multiple chip selects,but in the MSS, only one CS line is physically wired. To reflect this hardware limitation in the device tree, the binding enforces that the 'num-cs' property defaults to 1 and cannot exceed 1 unless additional chip select lines are explicitly defined using GPIO descriptors. Fixes: 2da187304e55 ("spi: add bindings for microchip mpfs spi") Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@xxxxxxxxxxxxx> --- .../bindings/spi/microchip,mpfs-spi.yaml | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml index 74a817cc7d94..19951951fdd6 100644 --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml @@ -13,9 +13,6 @@ description: maintainers: - Conor Dooley <conor.dooley@xxxxxxxxxxxxx> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: oneOf: @@ -43,6 +40,22 @@ required: - interrupts - clocks +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: microchip,mpfs-spi + not: + required: + - cs-gpios + then: + properties: + num-cs: + default: 1 + maximum: 1 + unevaluatedProperties: false examples: -- 2.25.1