On Thu, Jan 25, 2024, at 15:50, Tudor Ambarus wrote: > This will allow devices that require 32 bits register accesses to write > data in chunks of 8 or 16 bits. > > One SoC that requires 32 bit register accesses is the google gs101. A > typical use case is SPI, where the clients can request transfers in words > of 8 bits. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> My feeling is that this operation is rare enough that I'd prefer it to be open-coded in the driver than made generic here. Making it work for all corner cases is possible but probably not worth it. > +#ifndef writesb_l > +#define writesb_l writesb_l > +static inline void writesb_l(volatile void __iomem *addr, const void > *buffer, > + unsigned int count) > +{ > + if (count) { > + const u8 *buf = buffer; > + > + do { > + __raw_writel(*buf++, addr); > + } while (--count); > + } > +} > +#endif There are architectures where writesb() requires an extra barrier before and/or after the loop. I think there are others that get the endianess wrong in the generic version you have here. > +#ifndef iowrite8_32_rep > +#define iowrite8_32_rep iowrite8_32_rep > +static inline void iowrite8_32_rep(volatile void __iomem *addr, > + const void *buffer, > + unsigned int count) > +{ > + writesb_l(addr, buffer, count); > +} > +#endif This one is wrong for architectures that have a custom inl() helper and need to multiplex between inl() and writel() in iowrite32(), notably x86. For completeness you would need to add the out-of-line version in lib/iomap.c for those, plus the corresponding insb_32() and possibly the respective big-endian versions of those. If you keep the helper in a driver that is only used on regular architectures like arm64, it will work reliably. Arnd