On Thu, Jan 25, 2024 at 04:38:07PM +0000, Tudor Ambarus wrote: > On 1/25/24 16:16, Mark Brown wrote: > > Do we have any cases where we'd ever want to vary this independently of > > the SoC - this isn't a configurable IP shipped to random integrators? > The IP supports FIFO depths from 8 to 256 bytes (in powers of 2 I > guess). The integrator is the one dictating the IP configuration. In > gs101's case all USIxx_USI (which includes SPI, I2C, and UART) are > configured with 64 bytes FIFO depths. OK, so just the compatible is enough information then?
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