RE: [PATCH 1/2] spi: atmel: Do not cancel a transfer upon any signal

[David Laight <David.Laight@xxxxxxxxxx>]

...
> >> This calculation is actually wrong by factor 1000. A 20MHz SPI bus is not
> >> really slow and it will transfer ~2.5MB/s over a single lane.
> >> The calculation would be right for 20kHz but I think this is a more
> >> esoteric case, isn't it?
> >
> > Some of the sums are wrong, but the conclusion might be right.
> > A 4MB transfer at 20MHz only has 5 clocks/byte - seems low if it
> > is only using 1 data bit.
> 
> Can't really follow. Each data bit requires one clock on single wire
> SPI. Adressing and the like may require a bit of overhead but that
> should not be that much (12.5%?).

That is for 4MB in one second at 20MHz.

An SPI read transfer can be pretty much any length - you just keep
on clocking out data. The overhead is independent of the length.

A memory cell just reminded me that some SPI devices are made
of two (or more) memory blocks - and you can't do sequential
reads from one block to the next.
(It might be lying...)

	David

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