Hi Biju,
As per section 8.14 on the AT25QL128A hardware manual[1],
IO0..IO3 must be set to Hi-Z state for this flash for fast read quad
IO.
Snippet from HW manual section 8.14:
The upper nibble of the Mode(M7-4) controls the length of the next FAST
Read Quad IO instruction through the inclusion or exclusion of the
first
byte instruction code. The lower nibble bits of the Mode(M3-0) are
don't
care. However, the IO pins must be high-impedance before the falling
edge
of the first data out clock.
I'm still not sure what you are trying to fix here. For any quad I/O
mode,
the pins of the controller must be in hiZ during the data phase on a
read
operation. Otherwise the flash couldn't send any data, there would
be two drivers for one signal. So being in hiZ state should be the
default
and shouldn't depend on any connected flash.
You've mentioned the micron flash which needs a '1' on its hold/reset
pin. I would have expected a fixup for this flash, not for the flash
which
behaves normal.
-michael
