Re: [PATCH v7 2/2] spi: spi-geni-qcom: Add SPI Device mode support for GENI based QuPv3

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Hi,

With no knowledge of spi slave setup, I should say this looks good to me.

A few nits below which can be added in if there is going to be a v8, otherwise can be done later...



On 7/14/2023 9:52 AM, Praveen Talari wrote:
Currently spi geni driver supports only master mode operation.

Add spi device mode support to GENI based QuPv3.

Signed-off-by: Praveen Talari <quic_ptalari@xxxxxxxxxxx>
---
v6 -> v7:
- corrected author mail

v4 -> v5:
- added code comments
- dropped get_spi_master api.

v3 -> v4:
- Used existing property spi-slave.

v2 -> v3:
- modified commit message to use device mode instead of slave mode

v1 -> v2
- modified the commit message
- added the code changes for code comments
---
  drivers/spi/spi-geni-qcom.c | 53 ++++++++++++++++++++++++++++++++-----
  1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index 206cc04bb1ed..06b114f3f21a 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -12,6 +12,7 @@
  #include <linux/platform_device.h>
  #include <linux/pm_opp.h>
  #include <linux/pm_runtime.h>
+#include <linux/property.h>
  #include <linux/soc/qcom/geni-se.h>
  #include <linux/spi/spi.h>
  #include <linux/spinlock.h>
@@ -52,6 +53,9 @@
  #define SPI_CS_CLK_DELAY_MSK		GENMASK(19, 10)
  #define SPI_CS_CLK_DELAY_SHFT		10
+#define SE_SPI_SLAVE_EN (0x2BC)
+#define SPI_SLAVE_EN				BIT(0)
+

perhaps correct indentation here?

please check in an editor which uses correct number of spaces for a tab

  /* M_CMD OP codes for SPI */
  #define SPI_TX_ONLY		1
  #define SPI_RX_ONLY		2
@@ -99,6 +103,16 @@ struct spi_geni_master {
  	int cur_xfer_mode;
  };
+static void spi_slv_setup(struct spi_geni_master *mas)
+{
+	struct geni_se *se = &mas->se;
+
+	writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);
+	writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);
+	writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);
+	dev_dbg(mas->dev, "spi slave setup done\n");
+}
+
  static int get_spi_clk_cfg(unsigned int speed_hz,
  			struct spi_geni_master *mas,
  			unsigned int *clk_idx,
@@ -140,12 +154,22 @@ static void handle_se_timeout(struct spi_master *spi,
  	const struct spi_transfer *xfer;
spin_lock_irq(&mas->lock);
-	reinit_completion(&mas->cancel_done);

good to see reinit moved to after newly added goto

  	if (mas->cur_xfer_mode == GENI_SE_FIFO)
  		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
xfer = mas->cur_xfer;
  	mas->cur_xfer = NULL;
+
+	if (spi->slave) {
+		/*
+		 * skip CMD Cancel sequnece since spi slave
+		 * doesn`t support CMD Cancel sequnece

typo for sequence in 2 lines.

Or better, a more concise comment...

/* spi slave doesnt support CMD_CANCEL sequence */

+		 */
+		spin_unlock_irq(&mas->lock);
+		goto unmap_if_dma;
+	}
+
+	reinit_completion(&mas->cancel_done);
  	geni_se_cancel_m_cmd(se);
  	spin_unlock_irq(&mas->lock);
@@ -542,6 +566,10 @@ static bool geni_can_dma(struct spi_controller *ctlr,
  	if (mas->cur_xfer_mode == GENI_GPI_DMA)
  		return true;
+ /* Set SE DMA mode for SPI slave. */
+	if (ctlr->slave)
+		return true;
+
  	len = get_xfer_len_in_words(xfer, mas);
  	fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word;
@@ -619,6 +647,7 @@ static void spi_geni_release_dma_chan(struct spi_geni_master *mas) static int spi_geni_init(struct spi_geni_master *mas)
  {
+	struct spi_master *spi = dev_get_drvdata(mas->dev);
  	struct geni_se *se = &mas->se;
  	unsigned int proto, major, minor, ver;
  	u32 spi_tx_cfg, fifo_disable;
@@ -627,7 +656,14 @@ static int spi_geni_init(struct spi_geni_master *mas)
  	pm_runtime_get_sync(mas->dev);
proto = geni_se_read_proto(se);
-	if (proto != GENI_SE_SPI) {
+
+	if (spi->slave) {
+		if (proto != GENI_SE_SPI_SLAVE) {
+			dev_err(mas->dev, "Invalid proto %d\n", proto);
+			goto out_pm;
+		}
+		spi_slv_setup(mas);
+	} else if (proto != GENI_SE_SPI) {
  		dev_err(mas->dev, "Invalid proto %d\n", proto);
  		goto out_pm;
  	}
@@ -677,9 +713,11 @@ static int spi_geni_init(struct spi_geni_master *mas)
  	}
/* We always control CS manually */
-	spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
-	spi_tx_cfg &= ~CS_TOGGLE;
-	writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
+	if (!spi->slave) {
+		spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
+		spi_tx_cfg &= ~CS_TOGGLE;
+		writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
+	}
out_pm:
  	pm_runtime_put(mas->dev);
@@ -1072,6 +1110,9 @@ static int spi_geni_probe(struct platform_device *pdev)
  	pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
  	pm_runtime_enable(dev);
+ if (device_property_read_bool(&pdev->dev, "spi-slave"))
+		spi->slave = true;
+
  	ret = geni_icc_get(&mas->se, NULL);
  	if (ret)
  		goto spi_geni_probe_runtime_disable;
@@ -1092,7 +1133,7 @@ static int spi_geni_probe(struct platform_device *pdev)
  	 * for dma (gsi) mode, the gsi will set cs based on params passed in
  	 * TRE
  	 */
-	if (mas->cur_xfer_mode == GENI_SE_FIFO)
+	if (!spi->slave && mas->cur_xfer_mode == GENI_SE_FIFO)
  		spi->set_cs = spi_geni_set_cs;
ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);

Thank you...

-Vijay/





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