Re: [PATCH] spi: imx: correct handling of MXC_CSPIRXDATA value endianness

[Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>]

On 26.05.23 16:09, Ahmad Fatoum wrote:
>> -	writel(val, spi_imx->base + MXC_CSPITXDATA);
>> +	__raw_writel((__force u32)cpu_to_be32(val),
>> +		     spi_imx->base + MXC_CSPITXDATA);
>>  }

On more thing: __raw_writel doesn't involve a write barrier (at least
on ARM). That means above code introduces a bug as the CPU may now reorder
writes that were sequential before. Both iowrite32be() and readl()
have a __iowmb(); on ARM before doing the write itself.

>>  
>>  /* MX51 eCSPI */
>>
>>
>>
> 

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