Hi,
On 27/04/23 06:11, Yoshitaka Ikeda wrote:
Hi Dhruva,
Please can you send me the register fields information for the CQSPI
controller used in this device?
I wanted to verify if atall there were any mismatch between the controller I
have tested with vs your SOC's controller.
You can find it in the pdf that can be obtained by pressing the download button in the upper right corner of the following website.
- https://www.intel.com/content/www/us/en/docs/programmable/683126/15-0/introduction.html
Thanks for sharing, I went through and couldn't really find any major
changes at the controller level.
So I am wondering if some specific sequence of flash operations on your
device is exposing some issues in the driver's STIG reads.
Please can you share some logs with the following patch:
I am trying to see a pattern that may be causing issues.
I am unable to reproduce this on my end at the moment.
...
diff --git a/drivers/spi/spi-cadence-quadspi.c
b/drivers/spi/spi-cadence-quadspi.c
index 6ddb2dfc0f00..5fa71dbd37ef 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1390,6 +1390,14 @@ static int cqspi_exec_mem_op(struct spi_mem *mem,
const struct spi_mem_op *op)
int ret;
ret = cqspi_mem_process(mem, op);
+ /* debug */
+ printk("**********spi_mem_op dump**************");
+ printk("addr: nbytes:0x%X , buswidth 0x%X, dtr 0x%X, val
0x%llX", op->addr.nbytes, op->addr.buswidth, op->addr.dtr, op->addr.val);
+ printk("cmd: nbytes:0x%X , buswidth 0x%X, dtr 0x%X, opcode
0x%X", op->cmd.nbytes, op->cmd.buswidth, op->cmd.dtr, op->cmd.opcode);
+ printk("data: nbytes:0x%X , buswidth 0x%X, dtr 0x%X, data dir
0x%X", op->data.nbytes, op->data.buswidth, op->data.dtr, op->data.dir);
+
+ printk("***************************************");
+ /* ---------------------------- */
if (ret)
dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
...
--
Thanks and Regards,
Dhruva Gole
