AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and explicitly controls byte-lane enables. Signed-off-by: Brad Larson <blarson@xxxxxxx> --- v10 changes: - Move reset-names property definition next to existing resets prop - Move allOf to the bottom and set resets/reset-names required only for pensando - Fix reg maxItems for existing, must be 1 v9 changes: - Add reset-names and resets properties - Add if/then on property amd,pensando-elba-sd4hc to set reg property values for minItems and maxItems --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 33 ++++++++++++++++--- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index adacd0535c14..0c4d6d4b2b58 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -9,19 +9,18 @@ title: Cadence SD/SDIO/eMMC Host Controller (SD4HC) maintainers: - Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> -allOf: - - $ref: mmc-controller.yaml - properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -30,8 +29,13 @@ properties: maxItems: 1 resets: + description: physical line number to hardware reset the mmc maxItems: 1 + reset-names: + items: + - const: hw + # PHY DLL input delays: # They are used to delay the data valid window, and align the window to # sampling clock. The delay starts from 5ns (for delay parameter equal to 0) @@ -120,6 +124,27 @@ required: - interrupts - clocks +allOf: + - $ref: mmc-controller.yaml + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-sd4hc + then: + properties: + reg: + minItems: 2 + required: + - reset-names + - resets + else: + properties: + reset-names: false + resets: false + reg: + maxItems: 1 + unevaluatedProperties: false examples: -- 2.17.1