On Thu, Feb 09, 2023 at 01:13:21PM -0800, Vadim Fedorenko wrote: > Xilinx PG158 page 80 [1] states that master transaction inhibit bit must > be set to properly setup the transaction in QSPI mode. Add the force_irq > flag to follow this sequence. This doesn't apply against current code, please check and resend.
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