Re: [PATCH v2 7/9] dt-bindings: spi: mtk-snfi: Add read latch latency property

[Xiangsheng Hou (侯祥胜) <Xiangsheng.Hou@xxxxxxxxxxxx>]

Hi Angelo,

On Tue, 2022-12-06 at 13:19 +0100, AngeloGioacchino Del Regno wrote:
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/spi/mediatek,spi-
> > > > mtk-snfi.yaml
> > > > b/Documentation/devicetree/bindings/spi/mediatek,spi-
> > > > mtk-snfi.yaml
> > > > index bab23f1b11fd..6e6ff8d73fcd 100644
> > > > --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-
> > > > snfi.yaml
> > > > +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-
> > > > snfi.yaml
> > > > @@ -45,6 +45,13 @@ properties:
> > > >        description: device-tree node of the accompanying ECC
> > > > engine.
> > > >        $ref: /schemas/types.yaml#/definitions/phandle
> > > >    
> > > > +  mediatek,rx-latch-latency:
> > > > +    description: Rx delay to sample data with this value, the
> > > > value
> > > > +                 unit is clock cycle.
> > > 
> > > Can't we use nanoseconds or microseconds as a unit here, instead
> > > of
> > > clock cycles?
> > 
> > The clock cycle will be various with MediaTek SPI NAND controller
> > which
> > clock frequency can support 26/52/68/81/104MHz...
> > It`s may be easy to configure and understand with clock cycle in
> > unit.
> > 
> 
> Yes, but whatever clock frequency we use, the target is to always
> wait for
> X nanoseconds, right?
> 
> Waiting for 5 clock cycles at 104MHz is obviously not the same as
> waiting
> for the same 5 clock cycles at 26MHz: in that case, expressing the
> value
> in nanoseconds or microseconds would make that independent from the
> controller's clock frequency as the calculation from `time` to
> `cycles`
> would be performed inside of the driver.

There have two rx related timing properties in spi-peripheral-props.
The rx-sample-delay-ns have been used in Mediatek snfi driver to adjust
controller sample delay.
However another spi-rx-delay-us is in microseconds. Take 52MHz for
example, the clock cycle will be 19.23ns which lower than 1us. This may
not easy to by one clock cycle.

Thanks
Xiangsheng Hou