On Thu, Nov 17, 2022 at 09:47:41AM +0100, Carlo Caione wrote: > On some hardware (reproduced on S905X) when a large payload is > transmitted over SPI in bursts at the end of each burst, the clock line > briefly fluctuates creating spurious clock transitions that are being > recognised by the connected device as a genuine pulses, creating an > offset in the data being transmitted. > Lower the GPIO CS between bursts to avoid the clock being interpreted as > valid. This is just plain broken, *many* SPI devices attach meaning to chip select edges - for example register writes will typically have the register address followed by one or more register values for sequential registers. Bouncing chip select in the middle of transfer will corrupt data. If the device can't handle larger transfers it needs to advertise this limit and refuse to handle them.
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