Hi,
On 17/11/2022 09:47, Carlo Caione wrote:
On some hardware (reproduced on S905X) when a large payload is
transmitted over SPI in bursts at the end of each burst, the clock line
briefly fluctuates creating spurious clock transitions that are being
recognised by the connected device as a genuine pulses, creating an
offset in the data being transmitted.
Lower the GPIO CS between bursts to avoid the clock being interpreted as
valid.
I'm afraid this will actually break SPI NORs for example where CS actually splits
transactions.
Isn't Amjad change enough ? The CLK pull-up should avoid this.
If it's not the case, then it's an HW issue and the CLK line pull-up is too weak and an
external pull should then be added.
Signed-off-by: Carlo Caione <ccaione@xxxxxxxxxxxx>
---
drivers/spi/spi-meson-spicc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index d47f2623a60f..af8d74b53519 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -291,6 +291,10 @@ static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
static irqreturn_t meson_spicc_irq(int irq, void *data)
{
struct meson_spicc_device *spicc = (void *) data;
+ struct spi_device *spi_dev;
+
+ spi_dev = spicc->message->spi;
+ gpiod_set_value(spi_dev->cs_gpiod, 0);
writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
@@ -309,6 +313,8 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
/* Setup burst */
meson_spicc_setup_burst(spicc);
+ gpiod_set_value(spi_dev->cs_gpiod, 1);
+
/* Start burst */
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
