Re: [PATCH v2] spi: spi-imx: Fix spi_bus_clk if requested clock is higher than input clock

[Fabio Estevam <festevam@xxxxxxxxx>]

On Tue, Nov 15, 2022 at 1:27 PM Frieder Schrempf <frieder@xxxxxxx> wrote:
>
> From: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>
>
> In case the requested bus clock is higher than the input clock, the correct
> dividers (pre = 0, post = 0) are returned from mx51_ecspi_clkdiv(), but
> *fres is left uninitialized and therefore contains an arbitrary value.
>
> This causes trouble for the recently introduced PIO polling feature as the
> value in spi_imx->spi_bus_clk is used there to calculate for which
> transfers to enable PIO polling.
>
> Fix this by setting *fres even if no clock dividers are in use.
>
> This issue was observed on Kontron BL i.MX8MM with an SPI peripheral clock set
> to 50 MHz by default and a requested SPI bus clock of 80 MHz for the SPI NOR
> flash.
>
> With the fix applied the debug message from mx51_ecspi_clkdiv() now prints the
> following:
>
> spi_imx 30820000.spi: mx51_ecspi_clkdiv: fin: 50000000, fspi: 50000000,
> post: 0, pre: 0
>
> Fixes: 07e759387788 ("spi: spi-imx: add PIO polling support")
> Cc: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx>
> Cc: David Jander <david@xxxxxxxxxxx>
> Cc: Fabio Estevam <festevam@xxxxxxxxx>
> Cc: Mark Brown <broonie@xxxxxxxxxx>
> Cc: Marek Vasut <marex@xxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>

Thanks for the fix:

Tested-by: Fabio Estevam <festevam@xxxxxxxxx>