Re: [PATCH] spi: spi-imx: Revert "spi: spi-imx: add PIO polling support"

[David Jander <david@xxxxxxxxxxx>]

Dear Fabio,

On Fri, 11 Nov 2022 08:33:03 -0300
Fabio Estevam <festevam@xxxxxxxxx> wrote:

> Hi David,
> 
> On Fri, Nov 11, 2022 at 6:50 AM David Jander <david@xxxxxxxxxxx> wrote:
> 
> > The effect of this patch is that it will cause short SPI transfers to have a
> > lot less latency than without this patch, so could it be that we are looking
> > at a timing related bug in the MTD driver, or some other timing issue?
> > Your SPI clock is 80MHz, but the datasheet of the MACRONIX MX25R1635F
> > specifies a maximum clock of 33MHz. Is your NOR flash chip capable of this
> > clock-rate?  
> 
> Thanks for your suggestions.
> 
> I have tried passing spi-max-frequency = <33000000>, and I don't see
> the failure anymore.
> 
> Looking at the MX25R1635F datasheet the maximum SPI frequency is:
> 
> 80MHz: when L/H bit is 1 - High Performance mode.
> 33MHz: when L/H bit is 0 - Ultra Low Power mode.
> 
> "L/H switch bit The Low Power / High Performance bit is a volatile bit.
> User can change the value of L/H switch bit to keep Ultra Low Power
> mode or High Performance mode.
> Please check Ordering Information for the L/H Switch default support"

Oh, my bad, sorry. I didn't read far enough into the DS. I just wanted to point
out that AFAIK, if you use a clock higher than 33MHz, you probably also need
"m25p,fast-read" in the DT:

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/mtd/spi-nor/core.c#n2550

Not sure if that can cause the issues you are seeing though.

Best regards,

-- 
David Jander
Protonic Holland.