On Wed, Oct 12, 2022 at 12:21:35PM -0300, Mauro Lima wrote: > According to documentation, the 64K erase opcode is located in VSCC > range [16:23] instead of [8:15]. > Use the proper value to shift the mask over the correct range. > > Signed-off-by: Mauro Lima <mauro.lima@xxxxxxxxxxxxx> Reviewed-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
Re: [PATCH] spi: intel: Fix the offset to get the 64K erase opcode
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- Subject: Re: [PATCH] spi: intel: Fix the offset to get the 64K erase opcode
- From: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
- Date: Thu, 13 Oct 2022 11:41:30 +0300
- Cc: broonie@xxxxxxxxxx, linux-spi@xxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx
- In-reply-to: <20221012152135.28353-1-mauro.lima@eclypsium.com>
- References: <20221012152135.28353-1-mauro.lima@eclypsium.com>
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- [PATCH] spi: intel: Fix the offset to get the 64K erase opcode
- From: Mauro Lima
- [PATCH] spi: intel: Fix the offset to get the 64K erase opcode
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