On Fri, Sep 16, 2022 at 01:39:48PM +0200, Vincent Whitchurch wrote: > Add a test where a small and a large transfer in a message hit the same > cache line. This test currently fails on spi-s3c64xx on in DMA mode > since it ends up mixing DMA and PIO without proper cache maintenance. To make life easier with sending fixes as such fixes should come at the start of a patch series and new features at the end. This avoids creating spurious dependencies.
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