On 14/09/2022 15:17, Arnd Bergmann wrote:
On Wed, Sep 14, 2022, at 2:35 PM, Neil Armstrong wrote:
On 14/09/2022 13:19, Arnd Bergmann wrote:
On Tue, Sep 13, 2022, at 4:03 PM, Neil Armstrong wrote:
+ /* Sometimes, TC gets triggered while the RX fifo isn't fully flushed *
+ if (spicc->using_dma) {
+ unsigned int rxfifo_count = FIELD_GET(SPICC_RXCNT_MASK,
+ readl_relaxed(spicc->base + SPICC_TESTREG));
Same here in the interrupt controller, I don't see anything enforcing
the DMA to actually complete before the readl_relaxed().
I don't see the relathionship between a register relaxed read and the
DMA not finishing
writing the data in uncached memory, for me it's 2 unrelated things.
The race is between the readl_relaxed() and a subsequent access
to the data that is being transferred. On Arm processors you
need a "dmb(oshld)" instruction to ensure that the CPU cannot
prefetch data from the DMA buffer while it is waiting for the
MMIO to complete.
The __io_ar() in readl() exists specifically there for this race, and
this is the reason that readl_relaxed() exists for drivers that
do not do any DMA.
Acked, thx for for expliciting, will do the fix.
Note that this prefetching can happen for uncached memory, but
spe-meson-spicc uses cached memory.
Arnd
