Re: [PATCH v2 2/3] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers

[<Conor.Dooley@xxxxxxxxxxxxx>]

On 02/08/2022 08:05, Naga Sureshkumar Relli wrote:
> Add a driver for Microchip FPGA QSPI controllers. This driver also
> supports "hard" QSPI controllers on Polarfire SoC.
> 
> Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@xxxxxxxxxxxxx>
> ---
>   drivers/spi/Kconfig                   |   9 +
>   drivers/spi/Makefile                  |   1 +
>   drivers/spi/spi-microchip-core-qspi.c | 609 ++++++++++++++++++++++++++
>   3 files changed, 619 insertions(+)
>   create mode 100644 drivers/spi/spi-microchip-core-qspi.c
> 

---8<---

> +static int mchp_coreqspi_probe(struct platform_device *pdev)
> +{
> +	struct spi_controller *ctlr;
> +	struct mchp_coreqspi *qspi;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	int ret;
> +
> +	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*qspi));
> +	if (!ctlr)
> +		return dev_err_probe(&pdev->dev, -ENOMEM,
> +				     "unable to allocate master for QSPI controller\n");
> +
> +	qspi = spi_controller_get_devdata(ctlr);
> +	platform_set_drvdata(pdev, qspi);
> +
> +	qspi->regs = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(qspi->regs)) {
> +		ret = PTR_ERR(qspi->regs);
> +		goto remove_master;

Hey Suresh,

Since you switched to using devm_spi_alloc_master() these gotos are
no longer needed, and will cause a double put() of the controller.
devm_spi_alloc_master() should ensure that spi_controller_put() is
called in the case of a failure. You should just be able to return
dev_err_probe here & remove the remove_master label.

Thanks,
Conor.

> +	}
> +
> +	qspi->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(qspi->clk)) {
> +		dev_err(&pdev->dev, "clock not found.\n");
> +		ret = PTR_ERR(qspi->clk);
> +		goto remove_master;
> +	}
> +
> +	ret = clk_prepare_enable(qspi->clk);
> +	if (ret) {
> +		dev_err(&pdev->dev, "failed to enable clock\n");
> +		goto remove_master;
> +	}
> +
> +	init_completion(&qspi->data_completion);
> +	mutex_init(&qspi->op_lock);
> +
> +	qspi->irq = platform_get_irq(pdev, 0);
> +	if (qspi->irq <= 0) {
> +		ret = qspi->irq;
> +		goto clk_dis_all;
> +	}
> +
> +	ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr,
> +			       IRQF_SHARED, pdev->name, qspi);
> +	if (ret) {
> +		dev_err(&pdev->dev, "request_irq failed %d\n", ret);
> +		goto clk_dis_all;
> +	}
> +
> +	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
> +	ctlr->mem_ops = &mchp_coreqspi_mem_ops;
> +	ctlr->setup = mchp_coreqspi_setup_op;
> +	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
> +			  SPI_TX_DUAL | SPI_TX_QUAD;
> +	ctlr->dev.of_node = np;
> +
> +	ret = devm_spi_register_controller(&pdev->dev, ctlr);
> +	if (ret) {
> +		dev_err(&pdev->dev, "spi_register_controller failed\n");
> +		goto clk_dis_all;
> +	}
> +
> +	return 0;
> +
> +clk_dis_all:
> +	clk_disable_unprepare(qspi->clk);
> +remove_master:
> +	spi_controller_put(ctlr);
> +
> +	return ret;
> +}